Photolithography process in semiconductor manufacturing includes a process to pattern a photoresist. In this process, the photoresist is disposed on a substrate and exposed by a light through a photomask. The photomask includes a design pattern having main features formed according to a design layout of integrated circuits. After the exposure, the photoresist is developed to form a projected pattern therein same as the design patter of the photomask.
In the process, an optical proximity effect (OPE), which interferes the critical dimension (CD) of the linewidth of the projected pattern, may deviate the projected pattern formed on the photoresist from the design pattern of the photomask. Various optical proximity correction (OPC) techniques are utilized to decrease the deviation, such as simulating the design layout with an OPC model to from a corrected layout. Although existing process have been generally adequate for the intended purposes, it is not entirely satisfactory in all respects.